Power bipolar transistors carry and switch high current densities on a semiconductor chip with low losses. By applying a low steering current on the base, a significantly higher current is achieved between emitter and collector. Important in this context is the minimization of the resistance during switching, otherwise known as the saturation resistance, because it defines losses during switching. The thermal power dissipation limits the maximum current capable for the device and therefore defines the possible fields of application.
Contributions to the saturation resistance of a bipolar transistor include the doping profiles of base and emitter, the thickness of the epitaxial layer defining the breakdown voltage, and the ohmic contributions of emitter, base, and collector. In bipolar transistors, the base and emitter resistances may be optimized, because the base resistance contributes to the saturation resistance via the voltage drop and the field in the base. In field effect transistors (FET), different materials can be used for source and gate contacting without significant loss of performance. Poly-silicon layers may be used for gate-contacts of a FET. Poly-silicon has a lower conductivity compared to metal layers, but as the gate current can be neglected, the performance is acceptable with a significant advantage in terms of processability and lifetime stability.
Bipolar transistors contact base and emitter via low-ohmic metal layers, aiming at realization of a homogeneous, low ohmic connection of the active layers. Ohmic base and emitter resistances of bipolar transistors may be adjusted by varying the size of the contact area. When semiconductor size is constrained, the optimization of the ohmic emitter resistance of a bipolar transistor in the contact plane is limited due to the base contact and bond pad consuming a defined area on the semiconductor surface.
The present invention may address one or more of the above issues.